1. Technical Field
The present invention relates generally to an improved data processing system and in particular, the present invention relates to a method and apparatus for processing instructions. Still more particularly, the present invention relates to a method, apparatus, and computer processor design methodology for grouping instructions for execution.
2. Description of Related Art
A processor is the component in a data processing system that is used to execute instructions. Fundamentally, processors take signals in form of logic zeros and logic ones and manipulate these signals according to a set of instructions to produce an output in the form of logic zeros and ones. A processor contains various functional components. In particular, the processor contains execution units used to execute instructions. Additionally, a processor may include a branch predictor. This type of unit is used to guess the sequence in which instructions will be executed each time a program contains a conditional jump. This prediction is performed such that a pre-fetch or decode unit may obtain instructions in advance. Other types of units within a processor include, for example, a floating point unit, which performs non-integer type relations.
A processor also contains a level one cache, which is the cache closest to the processor. A level one cache is typically located within the processor core and may be implemented as a unified cache or separate sections for instruction and data. This L1 cache also is referred to as a primary or internal cache.
In executing instructions, currently available high-performance processor designs group instructions such that the instructions can be executed more efficiently. These grouped instructions are dispatched into queues for execution as a group. Instructions within a dispatch group will dispatch together and complete together.
Although this type of grouping provides for higher performance and more efficient instruction tracking, a critical path or bottleneck has been recognized by the present invention. When an incoming stream of instructions needs to be broken apart into special dispatch groups, these groups or formations allow the dispatch unit to send instructions to the execution units on a per-group basis. This logic is performed on-the-fly as the instructions are fetched from an instruction cache by an instruction fetch unit. The function for creating formations of groups take time. This type of dispatching adds pipeline delays to the processing of every instruction in these types of processor architectures.
Therefore, it would be advantageous to have an improved method, apparatus, and computer instructions for processing and grouping instructions.